Changeset 4673

Timestamp:

09/27/08 02:49:01 (5 years ago)

Author:

werner

Message:

Highlight:

• logic analyzer downloads are now about 66% faster

Details:

• lib/crc.py (crc.crc16): didn't even run
• lib/scope.py (rigol_la_data): only add data if it is different from the previous sample

Location:

developers/werner/ahrt/host/tmc/lib

Files:

• crc.py (modified) (1 diff)
• scope.py (modified) (1 diff)

developers/werner/ahrt/host/tmc/lib/crc.py

@@ -87 +87 @@
 
     def crc16(self, crc, bytes):
-        for b in bytes(crc, bytes):
+        for b in bytes:
             crc = (crc >> 8) ^ self.crc16_syndrome[(crc ^ b) & 0xff]
         return crc

developers/werner/ahrt/host/tmc/lib/scope.py

@@ -236 +236 @@
     for b in range(0, 16):
         res.append(digital())
+
+    prev_low = 0
+    prev_high = 0
+
     i = 424
     while i != 1624:
         div = (i-1024)/100.0
         t = t0+div*td
-        for b in range(0, 8):
-            res[b].append(t, (ord(s[i]) & (1 << b)) != 0)
-            res[b+8].append(t, (ord(s[i+1]) & (1 << b)) != 0)
+
+        doit = i == 424 or i == 1622
+
+        byte = ord(s[i])
+        if byte ^ prev_low or doit:
+            prev_low = byte
+            for b in range(0, 8):
+                res[b].append(t, (byte & (1 << b)) != 0)
+
+        byte = ord(s[i+1])
+        if byte ^ prev_high or doit:
+            prev_high = byte
+            for b in range(0, 8):
+                res[b+8].append(t, (byte & (1 << b)) != 0)
+
         i += 2
     return res