Ticket #46 (closed defect: fixed)
266MHz initialization of GTA01Bv2
| Reported by: | laforge@… | Owned by: | laforge@… |
|---|---|---|---|
| Priority: | high | Milestone: | |
| Component: | u-boot | Version: | current svn head |
| Severity: | major | Keywords: | |
| Cc: | buglog@… | Blocked By: | |
| Blocking: | Estimated Completion (week): | ||
| HasPatchForReview: | PatchReviewResult: | ||
| Reproducible: |
Description
The GTA01Bv2 and later have a 266MHz variant of the S3C2410. our current u-boot
code initializes it with 202MHz, though.
It is not as easy as only to reconfigure the PLL configuration. If we do that,
we only get a crash very early at bootup. Either invalid instruction or data abort.
We also need to increase CORE1V8 to 2.0 volts. Unfortunately our DC converter
in the PMU can only produce 1.8 or 2.1. Since the S3C2410 266 MHz specs say 2.0
+/- 0.1 volts, the 2.1 volts will do. I've done this temporarily by using "imw
0x08 0x21 0xe4, but that didn't help either.
I've checked the SDRAM timings, and even at the increased HCLK/MCLK/... they are
within specification. I2C also should definitely work.
It seems like it actually crashes somewhere in baudrate_init, before it gets to
serial_init. maybe some overflow.
Change History
comment:2 Changed 6 years ago by laforge@…
- Status changed from new to closed
- Resolution set to fixed
This is now part of u-boot. One can issue "neo1973 266MHz on" and it will
switch from 202MHz to 266MHz. Unfortunately the board crashes shortly later
because of what I assume are hardware issues. (see internal bugzilla Bug #75)
comment:3 Changed 6 years ago by laforge@…
With recent u-boot, the command has now changed to
"s3c2410 speed set 266"
which is more logical since the PLL is a parameter of the S3C2410 SoC, and not
the Neo1973 device.
Also, using GTA01Bv3 without FPC or debug board, it seems to run stable. I am
running "Linux fic-gta01 2.6.17.14-moko6 #65 Thu Feb 8 00:58:10 CET 2007 armv4tl
unknown" under 266/133/66 MHz speed, bogomips: 132.71
as it seems to me, there is some hardware problem causing random execution
failures of the CPU. has been reported to the hardware team.